This invention relates to a semiconductor memory device, more particularly, to an EEPROM (electrically erasable and programmable read only memory).
It is known that data can be read out of the EEPROM (hereinafter referred to as "the memory") generally at as high a speed as 100 nS to 200 nS. On the contrary, the writing of data in the memory can generally only occur at a speed between 1 mS to 50 mS. It has been found that the writing of data in parallel (i.e., a byte or a word) consumes almost as much time as the writing of an individual data bit, therefore the application of the parallel data-writing process can shorten data-writing time per byte. The length of time required to store one byte of data into a data storage is 200 nS, and the length of time required to transfer data from such a data storage to memory is about 1 mS. Therefore, the time required per byte, to store 16 bytes of data into memory as a unit will be (200 nS.times.16+1 mS).div.16, or about 63 .mu.S. Consequently the possibility of writing data in an extremely short period, as described above, is of great importance in the sense that EEPROMs can be applied in a very broad field.
With the conventional memory which is provided with the aforementioned memory storage function and enables data to be erased and written again, it is generally the case that, the route through which data is written and the route through which data is read out are provided independently. Consequently, the conventional memory has the drawback that the circuit arrangement is unavoidably complicated.
The above-mentioned conventional memory possesses a function of externally indicating whether the erasing of data and the programming thereof has been brought to an end. This function is referred to as "a data polling function". The conventional memory is equipped with a special control circuit in order to carry out said data-polling function. However, in this respect, too, the conventional memory has the drawback of a complicated circuit arrangement.